Level 3 Report

4 / 8 / 2025

TASK 1 : Digital DNA

Difference between Implementation code and Testbench code -

Implementation Code(DUT):

• This code describes the actual hardware design that will be synthesized and implemented on an FPGA or ASIC.
• This code must be synthesizable, meaning it can be translated into physical hardware components by a synthesis tool.
• It primarily uses synthesizable Verilog constructs posedge or negedge, assign, and module.

Testbench Code:

• This code is used to verify the functional correctness of the DUT.
• This code is generally not synthesizable. It is purely for simulation and verification purposes.
• It can use non-synthesizable constructs like initial blocks, fork-join, force, release, display, and file I/O operations.

8 bit signed Arithmetic Unit

An Arithmetic unit using Verilog is designed which gives result for addition, subtraction, comparison and absolute difference of two 8 bit signed numbers. I have also used the overflow, zero and negative flags.

Overflow flag - high when the result is out of the range

Zero flag - high when the result is zero

Negative flag - high when the MSB of result is 1

Here is the Github link to view the code.

Below is the image of the simulated waveform

4 bit Ripple Carry Adder

In Verilog, a generate block is used to replicate hardware structures (like repeating multiple instances of a module). 'genvar' is a special variable type in Verilog used inside a generate block.

Vivado or Quartus Prime does not allow the triple-delay format (rise, fall, turn-off). These FPGA tools are focused on synthesizable Verilog, not timing-accurate gate-level simulation. Hence, I have just designed the 4 bit Ripple carry adder using the generate block.

Here is the Github link to view the code.

Below is the simulated waveform -

2D Population Count Circuit

• matrix [15:0] : Flattened 4 X 4 matrix
• Each row count is 3 bits ([2:0]), max value = 4 if each element in the row is 1
• Each column count is also 3 bits.
• Total count is 5 bits ([4:0]) since max = 16

The image above depicts how the 2D Population Count works. The '2D' refers to the design which gives more than one type of result :

• Row-wise population count
• Column wise population count
• Total population cost

This design gives the statistics across two dimensions(row and column).

Here is the Github link to view the code.

Below is the image of the simulated waveform -

Capstone Home Light Automation

The design for this Home Light Automation was created using PLA in the previous level (Level 2 task 10). The same design is implemented in this task using the Verilog code with the same logic.

Here is the Github link to view the code files.

This is the simulated waveform -

In this, I have taken 5 test cases to showcase the result under each situation -

• Test Case 1: No motion, day, no override
• Test Case 2: Motion detected, dark, day
• Test Case 3: Motion detected, dark, night
• Test Case 4: Manual override ON
• Test Case 5: Random pattern is taken

Cellular Automation

A cellular automaton (CA) is a collection of cells arranged in a grid of specified shape, such that each cell changes state as a function of time, according to a defined set of rules driven by the states of neighboring cells.

Characteristics of a CA-

• The cells in a CA reside on a grid which has a specified shape (square, triangle, hexagon, etc.) and exist in a finite number of dimensions.
• Each cell on the grid has a state. The simplest state form is usually ON or OFF (or TRUE/FALSE or 1/0).
• Cells in a neighborhood affect each other, and each cell on the CA grid has a neighborhood.

Rule 90 -

Rule 90 is an elementary cellular automaton that consists of a one-dimensional array of cells, each of which can hold either a 0 or a 1 value. Each cell is the exclusive or(XOR) of its two neighbours.

If we concatenate the Next State into a single binary number and convert it to decimal (01011010) to the base 2, it becomes 90, hence we get the name Rule 90. When the initial state has a single nonzero cell, this diagram has the appearance of the Sierpiński triangle. Rule 90 is defined as: next_cell = left_neighbor XOR right_neighbor

The pattern looks like this.

Click here to view the code files.

The above image shows the simulated waveform. It can be seen that the output forms a serpinski triangle after many clock cycles.

TASK 2 : MOS Whisperer

CMOS Inverter

As seen in the previous level 1, task 6 , the CMOS inverter was implemented using LT SPICE. Similarly, the schematic and layout of the CMOS inverter is designed using Electric Binary. This is the schematic of inverter. It is similar to the implementation in LT SPICE.

This is the layout of the inverter. It has DRC(Design rule checks) and N well and P well check for the layout design. It ensures that all the active regions and wells are properly aligned and spaced out from the pmos and nmos.

The output waveform remains the same for both schematic as well as layout.

CMOS Operational Amplifier

I have implemented a single-stage CMOS operational amplifier based on a differential NMOS input pair with a PMOS active load in Electric VLSI. The two NMOS transistors form the input differential pair, receiving in+ and in– signals. The PMOS transistors are connected as a current mirror to act as active loads. The design provides output with a voltage gain with a phase inversion relative to the driven input transistor.

Above image shows the schematic of the opamp.

This image shows the transient analysis of the circuit. As it can be seen, a DC voltage is provided to the positive input (half of vdd) and a sine wave to the other negative input, resulting in an invetring opamp and the output has a voltage gain with a phase inversion.

This shows the ac analysis. It can be interpreted that the gain is ~21.97 dB (≈12.5×) and based on the roll ff, the BW is in the range of low MHz values. It has a Single-pole roll-off which is typical of single-stage designs.

This is the layout of the op amp. The output waveform is the same as that of schematic.

• Pink - contact cut (diffusion/poly to Metal1)
• Blue- polysilicon (gate layer)

TASK 3 : Logic Lore

FPGAs (Field Programmable Gate Arrays) are semiconductor devices that consist of a matrix of CLBs or customizable logic blocks linked by programmable interconnects. It is a semiconductor device that can be programmed and reconfigured after manufacturing to perform a wide variety of digital logic tasks.

FPGA consists of :

• I/O pads or I/O block
• Configurable Logic Block(CLB)
• Interconnects
• Switch Matrix

I/O Blocks -

• These blocks are surrounded by FPGAs in all 4 directions.
• It is used to communicate with external devices.

CLBs -

• CLB is a fundamental block or heart of FPGA
• The logic function is implemented in CLB
• CLB consists of : (a) LUT (b) D FF (c) MUX

(a) . Look Up tables

• It has maximum 4 inputs.
• It serves as basic truth tables mapping input combinations to output bits, enabling logic functions to be implemented.

(b). D Flip Flop

• Provides a delayed version of the output of LUT
• It stores state information, enabling the FPGA to create synchronous designs and pipelines.

(c). Multiplexer

• This 2 input MUX selects either the direct output or the delayed version of the output.

Interconnects -

• Used to connect the CLBs both horizontally and vertically.
• It basically transfers data among the CLBs

Switch Matrix-

• Each switch matrix point consists of six routing switches. -It sits between horizontal and vertical routing channels and decides which wires get connected together.
• The switch matrix’s job is to: Let signals change direction (horizontal ↔ vertical), Pass signals straight through, Allow branching (splitting one signal to multiple destinations), Keep some wires isolated to avoid short circuits.

Functioning- Think of it like a road junction:

• Roads = Routing wires.
• Traffic lights = Configuration bits.
• A green light lets a signal pass from one road to another; a red light blocks it.

Example:

• Signal comes from the east, needs to go north → The corresponding pass transistor between east and north wires is enabled.

• Six pass transistors are used for this purpose.

• The FPGA’s configuration memory (usually SRAM cells) holds control bits.

• The bitstream is loaded into the configuration memory and the switch matrix ensures signals enter and exit along the right wires to connect with other tiles.

Applications:

• Automotive
• FPGA based ASIC Prototyping
• Aerospace and Defence
• Consumer electronics
• Wired and Wireless communications

TASK 4 : Silicon Sandbox

As seen in the previous task, a single FPGA tile has different components each performing a specific task. The FPGA tile behaviour can be implemented in the form of a Verilog code.

Click here to view the code files.

Here, the overall architecture of a single FPGA tile with all the components(CLB with it's D ff, MUX and LUT, and the Switch matrix along with the inputs and outputs) is shown.

Working -

---> Direct LUT output (d_ff =0)

• CLB_out = lut_out directly, no delay.
• lut_out = in3 ^ in2 ^ in1 ^ in0
• config_sw = {2'd3, 2'd3, 2'd3, 2'd3} means each output of the SwitchMatrix takes sw_inputs[3] , i.e. CLB_out
• out_signals = {CLB_out, CLB_out, CLB_out, CLB_out}

The above table shows what values the output signals must have according to the input signals given

This is how the simulated waveform will look like.

---> D ff delayed output (d_ff = 1)

• CLB_out = ff_out
• ff_out <= lut_out on posedge clk
• the output is one clock late — it shows the LUT result from the previous input as it can be seen from the simulated waveform below

TASK 5 : The Great Timing Heist