COURSE

VLSI-FG-001

3 Levels · 8 Months

A focus group on VLSI

Level 1

Task 0.1: Linux Basics & LibreCell/aicex Installation

Digital

Task Description: Set up Linux development environment and install LibreCell toolchain. Learn Linux command-line basics, file system navigation, environment variables, and package management. Install and configure LibreCell dependencies including Yosys, OpenROAD, Magic, and verify all tools are working correctly.

Resource Links:

Platform: Linux (Ubuntu 20.04 or later) / WSL / VM

Deliverables / Outcomes:

Screenshot/log showing successful installation of all LibreCell tools
Functional project directory structure with README documenting setup steps
Verified tool installations with basic command outputs (yosys --version, openroad --version, etc.)

Analog

Set up the aicex (Analog IC design EXperience) toolchain for MARVEL's VLSI domain to enable open-source analog IC design workflows on the SKY130 PDK. This forms the foundational environment for future tapeout projects and member onboarding.

Steps:

Install system dependencies (Magic, Netgen, Xschem, ngspice) on the target machine (Ubuntu 22.04/24.04)
Clone and install aicex, cicsim, and cicconf from the Wulff/analogicus repos
Install Sky130A/B PDK via volare
Configure cicconf project environment and verify PDK paths.

Resource Links: The analog toolchain

Task 0.2: SPI Protocol Fundamentals

Task Description: Understand SPI communication protocol in detail. Study clock phases (CPOL/CPHA), the four SPI mode combinations (0,0 / 0,1 / 1,0 / 1,1), master-slave interaction, chip select behavior, and data serialization. Create detailed timing diagrams and comparison tables for all modes.

Resource Links:

Platform: Documentation / Diagram tools (draw.io, Lucidchart, or pen & paper)

Deliverables / Outcomes:

Timing diagrams for all four SPI modes
SPI mode comparison table (CPOL, CPHA, behavior for each mode)
Detailed 8-bit transaction timing diagram for Mode 0 (MSB-first)
SPI protocol reference sheet documenting setup/hold times and constraints

Task 0.3: Architecture & Block Design

Task Description: Decompose SPI controller into functional blocks. Identify shift register, clock divider, FSM, control logic, and system interface. Create block diagram with all interconnections, define data flow and control flow, and document architectural decisions (full-duplex, 8-bit fixed transactions, MSB-first, reset/abort handling, back-to-back transaction support).

Resource Links:

Platform: Diagram tools (draw.io, Lucidchart, or similar)

Deliverables / Outcomes:

Block diagram with all blocks labeled, signals named (with widths and directions)
Architecture decision document (1-2 pages) explaining design choices
Data flow diagram showing how data moves through blocks
Block responsibility matrix defining each block's inputs, outputs, and purpose

Task 0.4: Port & Signal Specification

Task Description: Define complete interface contract for SPI controller. Specify all system I/O signals (CLK, RST_N, SPI_MODE, DIV_RATIO, DATA_IN, TX_VALID, DATA_OUT, RX_VALID, TX_READY, BUSY) and SPI pins (SCK, MOSI, MISO, CS_N). Document signal widths, active levels, timing constraints, and relationships between signals.

Resource Links:

Platform: Documentation / Spreadsheet

Deliverables / Outcomes:

Signal specification table (register-map style) with widths, directions, active levels
Timing constraint list with diagrams
Complete protocol timing diagram showing multiple 8-bit transactions
Signal relationship matrix documenting when each signal is valid

Task 0.5: FSM & Control Logic Design

Task Description: Design finite state machine for SPI controller with states: IDLE (waiting), ACTIVE (shifting data), and DONE (transaction complete). Define transitions, handle reset behavior, back-to-back transactions, and abort scenarios. Create state transition diagrams and output truth tables.

Resource Links:

Platform: Diagram tools / Documentation

Deliverables / Outcomes:

State transition diagram (bubble diagram with labeled transitions and conditions)
State-output truth table mapping states to control signals (SCK, MOSI, CS_N, RX_VALID, etc.)
FSM pseudocode or detailed description of state machine behavior
Timing diagram showing state progression for multiple sequential transactions

Task 0.6: RTL Translation

Task Description: Translate design specifications into synthesizable Verilog. Implement all blocks (shift register, clock divider, FSM, control logic) and system interface. Write clean, well-commented RTL that directly maps to the design from Tasks 0.2-0.5. Ensure proper reset behavior, clock synchronization, and signal naming consistency.

Resource Links:

Platform: Verilog / Text Editor

Deliverables / Outcomes:

Complete synthesizable Verilog file(s) for SPI controller (all modules)
Design document mapping RTL code sections to specification
Verilog syntax verification (compiles with no errors)
Code comments explaining non-obvious logic sections

Task 0.7: The PN Junction and Diode

Objective: Understand the fundamental two-terminal device that underlies every MOSFET body diode and ESD structure. Platform: Theory + Simulation (ngspice)

Theory

P-type and n-type doping, depletion region formation, built-in potential $V_{bi}$
Forward and reverse bias — what happens to depletion width in each case
The Shockley equation:

$$ I_D = I_S\left(e^{V_D/nV_T} - 1\right) $$

Know what $I_S$, $n$, and $V_T = kT/q \approx 26,\text{mV}$ mean physically

Breakdown: Zener (tunneling, low voltage) vs. avalanche (impact ionization, high voltage)
Dynamic resistance $r_d = V_T/I_D$ — smaller at higher current

Simulation

Build the following in ngspice using a 1N4148 model:

Clipper circuit — place a diode in parallel with the load resistor. Drive it with a sine wave and observe how the output is clipped at $\approx 0.7,\text{V}$ on one half-cycle

Clamper circuit — place a diode in series with a capacitor to shift the DC level of a waveform. Observe how the output baseline shifts after a few cycles

Deliverables

Hand-sketched I–V curve with cutoff, forward conduction, and breakdown regions labeled
Calculated $r_d$ at $1,\text{mA}$ and $10,\text{mA}$
Clipper and clamper simulation waveforms with input and output overlaid
One paragraph: where do body diodes appear in a CMOS layout and why do they matter?

Task 0.8: The BJT

Objective: Understand the bipolar junction transistor and why it still appears in precision analog despite CMOS dominance. Platform: Theory + Simulation (ngspice)

Theory

Physical structure: emitter, base, collector; NPN vs. PNP
Three operating regions: cutoff, active (forward-active), saturation — identify each from terminal voltages
Collector current in active region:

$$ I_C = I_S, e^{V_{BE}/V_T} $$

The exponential dependence on $V_{BE}$ is both the strength of the BJT (predictable $V_{BE}$ reference) and its sensitivity (temperature drift)

Current gain $\beta = I_C/I_B$ and transconductance $g_m = I_C/V_T$
Key insight: $g_m$ is set purely by bias current — there is no $W/L$ knob like in a MOSFET. This gives BJTs higher $g_m$ per unit current, which is why they appear in bandgap references and low-noise front ends
The dioden3v device in TSMC 180nm is a substrate PNP used in diode-connected configuration — this is exactly how a bandgap reference generates a stable $V_{BE}$

Simulation

Common-emitter amplifier — bias an NPN into active region with a resistor divider. Apply a small AC input at the base and measure voltage gain at the collector. Verify that $A_v \approx -g_m R_C$ matches your hand calculation.

Deliverables

Table: MOSFET vs. BJT — controlling terminal, current equation, $g_m$ expression, key advantage, key weakness
CE amplifier schematic + AC simulation plot with midband gain annotated
2–3 sentences: why does a bandgap reference use a BJT rather than a MOSFET for the voltage reference element?

Task 0.9: The MOSFET

Objective: Understand the device that every analog and digital circuit in this domain is built from
Platform: Theoretical

The MOSFET is the fundamental building block of modern electronics. Before you simulate, lay out, or tape out anything, you need to know what you are working with.

Cover the following:

Physical structure: gate, source, drain, body and what each terminal actually controls
The operating regions: cutoff, triode (linear), saturation and how to identify which region a transistor is in from its terminal voltages
The drain current equation in saturation:

$$ I_D = \frac{1}{2} \mu_n C_{ox} \frac{W}{L} (V_{GS} - V_{TH})^2 $$

Understand what each term means physically especially why the $\frac{W}{L}$ ratio is the primary design knob for analog designers

NMOS vs PMOS: how they complement each other and why "CMOS" logic uses both
Why MOSFETs replaced BJTs as the dominant device in integrated circuit design

Resources:

Razavi Electronics 1, Lec 29 — Intro to MOSFETs
Behzad Razavi, “Design of Analog CMOS Integrated Circuits”, 2nd Edition.

Task 0.10: Second-Order MOSFET Effects

Objective: Move beyond the square-law and understand real device behavior you will see in every simulation. Platform: Theory

Channel Length Modulation

In saturation, $I_D$ is not truly constant with $V_{DS}$. The actual expression is:

$$ I_D = \frac{1}{2}\mu_n C_{ox}\frac{W}{L}(V_{GS}-V_{TH})^2,(1+\lambda V_{DS}) $$

$\lambda$ is larger for short-channel devices, meaning $r_o = 1/\lambda I_D$ is smaller — short transistors are poor current sources.

Velocity Saturation

At short channel lengths, the carrier velocity hits a limit before pinch-off occurs. The result: $I_D$ becomes more linear in $(V_{GS} - V_{TH})$ rather than quadratic. This is the physical reason the 14nm FinFET $g_m$ and $f_T$ increase with temperature — velocity-saturation-dominated transport, not the long-channel drift picture.

Body Effect

When the source is not tied to the bulk (e.g. in a cascode stack), $V_{SB} > 0$ raises $V_{TH}$:

$$ V_{TH} = V_{TH0} + \gamma\left(\sqrt{2\phi_F + V_{SB}} - \sqrt{2\phi_F}\right) $$

This shifts the operating point and is a common source of simulation surprises in stacked topologies.

Subthreshold Conduction

Below $V_{TH}$, the drain current does not abruptly go to zero — it falls exponentially. The subthreshold slope is $\approx 60,\text{mV/decade}$ at room temperature. This is a fundamental physical limit (not a process limitation) and is the reason supply voltages cannot scale arbitrarily low.

Mismatch (Pelgrom)

Two nominally identical transistors on the same die will have slightly different $V_{TH}$:

$$ \sigma(\Delta V_{TH}) = \frac{A_{VT}}{\sqrt{WL}} $$

Larger devices match better. A diff pair with $4\times$ the area has only $2\times$ better matching — the $\sqrt{WL}$ dependence is why area in analog layout is never free.

Deliverables

Hand-sketched $I_D$–$V_{DS}$ family of curves showing finite output slope due to $\lambda$
One paragraph each on velocity saturation and subthreshold slope in your own words
Explain in 2–3 sentences why Pelgrom's law means $4\times$ area gives only $2\times$ matching improvement

Task 0.11: The CMOS Inverter

Objective: Understand the most fundamental CMOS gate and why it is the gateway drug to everything in digital and analog IC design. Platform: Theory + Simulation (ngspice)

Theory

Why complement each other: NMOS pulls down, PMOS pulls up — when one is ON the other is OFF, so static power is nearly zero (unlike pure NMOS or RATIOED logic)
DC transfer characteristic (VTC): identify the five regions as $V_{in}$ sweeps from 0 to $V_{DD}$
Switching threshold $V_M$ — the $V_{in}$ at which $V_{out} = V_{in}$. For a symmetric inverter $V_M \approx V_{DD}/2$; shifting $W/L$ ratios moves it
Noise margins $NM_H$ and $NM_L$ — how much voltage noise the inverter can tolerate before misreading a logic level
Dynamic behavior: $t_{pHL}$ and $t_{pLH}$ are set by how fast the output capacitance charges and discharges through the PMOS and NMOS respectively

Simulation

DC sweep — sweep $V_{in}$ from 0 to $V_{DD}$ and plot the VTC. Identify $V_M$, $NM_H$, $NM_L$, and the high-gain region. Vary the PMOS $W/L$ and observe how $V_M$ shifts.

Transient — drive the inverter with a pulse input and measure $t_{pHL}$ and $t_{pLH}$ on the output. Observe the short-circuit current spike during switching when both transistors are momentarily on.

Task 0.12: Introduction to Operational Amplifiers

Objective: Understand the most versatile analog building block and simulate one before Level 1
Platform: Theory + Xschem/ngspice

Part 1 — Theory

What an ideal op-amp is: infinite open-loop gain, infinite input impedance, zero output impedance
The virtual ground concept and why it makes op-amp circuit analysis tractable
Negative feedback: what it does to gain, bandwidth, and stability
The difference between open-loop and closed-loop behaviour
Gain-bandwidth product why you cannot have infinite gain at all frequencies simultaneously

Part 2 — Simulation

Using a standard op-amp SPICE model (LM741), simulate a basic inverting amplifier in ngspice
Set a closed-loop gain of -10 and verify with an AC simulation
Plot the frequency response: identify the -3dB point and observe the gain-bandwidth product
This is your first Xschem simulation using a generic SPICE model. Your first SKY130 simulation comes in A1.

Resources:

ngspice quickstart

Level 2

Level 1 — Analog Track: Deep circuit intuition

A1. First Steps: MOS Amplifiers

Objective: Get comfortable with Xschem and ngspice by building your first real VLSI circuits, and understand all three fundamental single-transistor amplifier configurations
Prerequisite: Level 0 complete

Setup

Install and configure the SkyWater 130nm PDK
Configure Xschem to find the PDK libraries
- Explore the demo schematics bundled with the PDK, get a feel for the interface before building your own

Task

Common-Source (CS) Amplifier

Design a CS amplifier with proper DC biasing in Xschem using SKY130 transistors
Run transient and AC simulations in ngspice
Measure and record: voltage gain, input impedance, output impedance, -3dB bandwidth
Understand: inverting gain Av=−gmroA_v = -g_m r_o Av=−gmro, high input impedance, dominant pole set by CgdC_{gd} Cgd via Miller effect

Common-Gate (CG) Amplifier

Design a CG amplifier — input at source, output at drain, gate is the AC ground
Run the same set of simulations
Measure and record: voltage gain, input impedance, output impedance, -3dB bandwidth
Understand: non-inverting gain Av=gmroA_v = g_m r_o Av=gmro, low input impedance (≈1/gm\approx 1/g_m ≈1/gm), no Miller effect on CgdC_{gd} Cgd — why this makes it useful at high frequencies

Common-Drain (CD) Amplifier — Source Follower

Design a CD amplifier — input at gate, output at source, drain is the AC ground
Run the same set of simulations
Measure and record: voltage gain, input impedance, output impedance, -3dB bandwidth
Understand: gain slightly less than 1, very high input impedance, very low output impedance (≈1/gm\approx 1/g_m ≈1/gm) — why this makes it the go-to buffer stage

Comparison

Build a side-by-side table: gain, input impedance, output impedance, bandwidth, inverting/non-inverting. Understand when you would choose each topology.

What to understand: CS, CG, and CD are the three fundamental single-transistor configurations — every analog circuit you will ever see is built from combinations of these. CS gives gain. CG extends bandwidth. CD buffers. Together they form the cascode (CS+CG) and the telescopic/folded structures in A4. This is your first simulation using real SKY130 PDK device models.

Resources:

Xschem documentation
Behzad Razavi, “Design of Analog CMOS Integrated Circuits”, 2nd Edition.
Razavi YT channel (Long Kong)

A2. CS Amplifier Variants

Objective: Understand why different CS amplifier topologies exist and when to use each one
Prerequisite: A1

Design and simulate each of the following CS amplifier load topologies in Xschem/ngspice:

Topology	Key characteristic
Resistive load	Simplest — gain limited by voltage headroom
Diode-connected load	Self-biasing — lower gain, predictable
Active load (PMOS current mirror)	High gain — the workhorse of analog design
Current source load	Maximum output impedance — maximises gain
Triode load	Understand the trade-offs vs saturation-region loads

For each topology:

Draw the small-signal equivalent circuit by hand and derive the voltage gain expression
Build and simulate in Xschem/ngspice. Verify your hand calculation matches simulation
Record: gain, output swing, power consumption

Deliverable: A written comparison table covering gain, practical use case for all five topologies, etc.

What to understand: Why the active load is used in virtually every real op-amp differential pair. How the PMOS current mirror simultaneously provides high output impedance and sets the bias current.

Resources:

Behzad Razavi, “Design of Analog CMOS Integrated Circuits”, 2nd Edition.
Razavi YT channel (Long Kong)

A3. Current Mirrors

Objective: Understand the current mirror - the bias and load circuit used in almost every analog IC
Prerequisite: A2

A current mirror copies a reference current to one or more output branches. It is how analog circuits set and distribute bias currents across a chip without resistors. Understanding current mirrors deeply is non-negotiable before tackling differential amplifiers or op-amp design.

Tasks

Design, simulate, and compare the following current mirror topologies in Xschem/ngspice:

Topology	What it improves
Basic current mirror	Baseline — understand output impedance and current error
Cascode current mirror	Higher output impedance — understand why stacking transistors helps
Wilson current mirror	Feedback-based improvement — analyse the feedback loop
Wide-swing cascode mirror	Maximum output swing without sacrificing output impedance

For each topology:

Derive the small-signal output impedance by hand
Simulate output current vs output voltage (I-V curve) — measure output impedance from the slope
Measure current copying error vs the reference — understand what causes it

What to understand: Why output impedance of the mirror directly determines gain when used as an active load. The trade-off between output impedance and output voltage swing.

Resources:

Behzad Razavi, “Design of Analog CMOS Integrated Circuits”, 2nd Edition.
Razavi YT channel (Long Kong)

A4. Cascode Amplifiers

Objective: Understand how cascoding boosts gain and output impedance beyond what a single transistor can achieve
Prerequisite: A2, A3

Tasks

Part 1 — Telescopic Cascode

Design a telescopic cascode amplifier in Xschem/ngspice
Derive the voltage gain and output impedance expressions by hand — verify with simulation
Understand why gain scales as (gm·ro)² and what this means in practice
Identify the headroom problem — why telescopic cascodes sacrifice output swing

Part 2 — Folded Cascode

Design a folded cascode amplifier — understand how folding resolves the headroom issue
Compare voltage gain, output impedance, output swing, and power consumption between telescopic and folded versions
Understand when you would choose one over the other

What to understand: The cascode transistor as a shield — it presents high impedance to the output while keeping the lower transistor in saturation. Why the folded cascode is preferred in low-voltage designs.

Resources:

Behzad Razavi, “Design of Analog CMOS Integrated Circuits”, 2nd Edition.
Razavi YT channel (Long Kong)

A5. Differential Amplifiers

Objective: Understand the differential pair: The input stage of every op-amp and comparator ever designed
Prerequisite: A3, A4

Tasks

Part 1 — Basic Differential Pair

Design a basic NMOS differential pair with resistive loads in Xschem/ngspice
Simulate differential gain and common-mode gain
Calculate and verify CMRR (Common Mode Rejection Ratio) — understand what it means and why it matters
Understand the role of the tail current source in determining CMRR

Part 2 — Differential Pair with Active Load

Replace resistive loads with a PMOS current mirror active load (from A3)
Observe how gain increases dramatically — understand why
Simulate the differential-to-single-ended conversion happening at the output
Measure offset voltage and understand its sources

Part 3 — Analysis

Draw the small-signal half-circuit model by hand
Derive differential gain, common-mode gain, and CMRR analytically
Verify all three against your ngspice simulation

What to understand: Why the differential pair is ubiquitous. How it rejects noise that appears on both inputs simultaneously. Why the active load is essential for high gain.

Resources:

Behzad Razavi, “Design of Analog CMOS Integrated Circuits”, 2nd Edition.
Razavi YT channel (Long Kong)

A6. Negative Feedback Systems

Objective: Understand negative feedback as a system-level concept — the idea that unifies almost every analog circuit you will ever design

Before you can understand why a two-stage op-amp needs Miller compensation, or why a current mirror has finite output impedance, or why a diff pair rejects common-mode signals — you need to understand feedback. This task builds that foundation.

Part 1 — The Feedback Framework

Identify the four components of any feedback system: forward gain block $A$, feedback network $f$, summing junction, output
Closed-loop gain: $A_{CL} = \frac{A}{1 + Af}$ — understand what happens as $A \to \infty$
Loop gain $T = Af$ — this single quantity determines stability, sensitivity, and distortion reduction
Why negative feedback desensitises gain to process variation: $\frac{dA_{CL}}{A_{CL}} \approx \frac{1}{1+T} \cdot \frac{dA}{A}$
The four feedback topologies (series-shunt, shunt-series, series-series, shunt-shunt) and what each one controls at input and output

Part 2 — Stability

Why feedback systems can oscillate: phase shift accumulates around the loop until negative feedback becomes positive
The Barkhausen criterion: oscillation occurs when $|Af| = 1$ and $\angle Af = -180°$
Phase margin from the Bode plot — how to read it and what it tells you about transient response
Gain margin — the other stability metric
Simulate the loop gain of your differential pair from A5 using the .ac analysis. Extract phase margin directly.

Part 3 — Connecting Back to Circuits

Identify the feedback topology in: an inverting op-amp, a source follower, a CS amplifier with source degeneration
Explain in each case what quantity is being regulated and what the loop gain is
Understand why the Wilson current mirror (A4) has better output impedance than the basic mirror — it uses feedback

What to understand: Feedback is not a trick. It is the central organizing principle of analog design. Every circuit you build from here either uses feedback deliberately or is affected by parasitic feedback unintentionally.

Resources:

Behzad Razavi, "Design of Analog CMOS Integrated Circuits", 2nd Edition — Chapter 8
Prof. Nagendra Krishnapura, IIT Madras — Analog Circuits (NPTEL)
Razavi YT channel (Long Kong)

A7. Frequency Response

Objective: Understand how and why amplifier gain degrades with frequency
Prerequisite: A4, A5

Frequency response is what separates a circuit that works at DC from one that works at 100MHz. Every pole and zero in your circuit has a physical cause. This task teaches you to find them and understand them.

Tasks

Part 1 — Poles and Zeros

Understand what a pole is physically — a frequency where gain starts to roll off
Identify the dominant pole in your CS amplifier from A1 — where does it come from physically?
Run AC simulation and identify poles from the Bode plot
Verify with hand calculation using the time-constant method

Part 2 — Miller Effect

Understand the Miller effect — how a feedback capacitance ($C_{gd}$) appears multiplied at the input
Calculate the Miller capacitance for your CS amplifier
Observe its effect on bandwidth in simulation — compare with and without Miller approximation
Understand why the Miller effect is both a problem (bandwidth reduction) and a tool (compensation)

Part 3 — Frequency Response of the Differential Pair

Extend the differential pair from A5 with parasitic capacitances
Identify the non-dominant pole introduced by the current mirror load
Simulate the Bode plot and locate both poles

What to understand: Every real circuit has poles. Knowing where they are and what causes them is how you design amplifiers that are fast and predictable.

Resources:

Behzad Razavi, "Design of Analog CMOS Integrated Circuits", 2nd Edition.
Razavi YT channel (Long Kong)

A8. Op-Amps — For Real This Time

Objective: Revisit the op-amp not as a black box but as a circuit you can now fully analyse and design from transistors up
Prerequisite: A7

In Task 0.12 you used an op-amp as a given. Now you know what is inside. The diff pair (A5) is the input stage. The cascode or CS stage (A3/A4) provides the second gain stage. Miller compensation (A9) stabilises the loop. Everything converges here.

Part 1 — The Two-Stage Op-Amp

Identify the two gain stages: differential pair with active load → common-source output stage
Analyse DC operating point: how bias currents flow through both stages
Derive open-loop gain: $A_{OL} = g_{m1}(r_{o2} | r_{o4}) \cdot g_{m6}(r_{o6} | r_{o7})$
Understand the role of each transistor — nothing is there by accident
Simulate open-loop AC response. Identify the two poles and measure open-loop gain.

Part 2 — Compensation

Add the Miller compensation capacitor $C_c$ between the output of stage 1 and stage 2
Observe pole splitting: dominant pole moves lower, non-dominant pole moves higher
Measure phase margin before and after compensation
Understand the RHP zero introduced by $C_c$ and why it degrades phase margin — and how a nulling resistor fixes it

Part 3 — Closed-Loop Behaviour

Close the loop in unity-gain configuration and simulate step response
Measure slew rate — understand why it is limited by the tail current and $C_c$
Simulate closed-loop bandwidth and verify it equals the GBW product
Run a corner simulation: SS, TT, FF corners at -40°C and 125°C. Observe how gain and bandwidth shift.

What to understand: The op-amp is not a component. It is a design methodology — a high-gain block wrapped in feedback to make a predictable, stable, process-insensitive amplifier. You now have all the tools to design one from scratch, which is exactly what A11 asks you to do.

Resources:

Behzad Razavi, "Design of Analog CMOS Integrated Circuits", 2nd Edition — Chapters 9, 10
Prof. Nagendra Krishnapura, IIT Madras — Analog Circuits (NPTEL)
Razavi YT channel (Long Kong)

A9. Stability, Compensation, and Noise

Objective: Understand how to make amplifiers stable and how noise sets the sensitivity floor
Prerequisite: A6

Part 1: Stability and Dominant Pole Compensation

Understand phase margin — why it predicts whether a feedback amplifier will oscillate
Simulate phase margin on your differential pair from A6
Add a Miller compensation capacitor and observe how it pushes the dominant pole lower and improves phase margin
Understand the gain-bandwidth product trade-off — compensating for stability costs bandwidth

Part 2: Noise Fundamentals

Noise is what limits every analog circuit at the bottom end. You cannot fix it in post.

Thermal noise: resistors and channel resistance generate $\overline{v_n^2} = 4kTR,\Delta f$ — white, unavoidable, scales with temperature and resistance
Flicker (1/f) noise: dominant at low frequencies in MOSFETs; arises from carrier trapping at the oxide interface; PMOS typically has lower flicker noise than NMOS in SKY130
Input-referred noise: the standard way to compare amplifier noisiness — reflect all internal noise sources back to the input as an equivalent $v_{n,in}$
For a CS amplifier: $\overline{v_{n,in}^2} \approx \frac{4kT\gamma}{g_m} + \frac{K}{C_{ox}WLf}$ — understand what each term depends on and how to reduce it
Simulate noise in ngspice using .noise analysis on your CS amplifier. Plot input-referred noise spectral density vs frequency. Identify the 1/f corner frequency.

What to understand: Stability and noise bound every analog design from above and below. Phase margin keeps it from oscillating; noise floor keeps it from being useful at small signals.

Resources:

Behzad Razavi, "Design of Analog CMOS Integrated Circuits", 2nd Edition.
Razavi YT channel (Long Kong)

Synthesized netlist (Verilog gate-level or DEF format)
Synthesis report (area, cell counts, resource usage)
Timing analysis report (critical paths with slack values, delay breakdown)
Timing constraint file defining requirements
If optimized: updated netlist with improved timing
Sign-off report: "All timing violations closed with Xns slack"

Level 3

Level 2 Analog Track: Layout and Tapeout

A10. Magic! Your First Layout

Objective: Translate a schematic into a physical layout for the first time — understand what a circuit actually looks like on silicon
Prerequisite: Level 1 Analog complete

Part 1: Learn Magic

Learn the Magic interface: layer palette, DRC error markers, cell hierarchy, extraction
Understand the SKY130 layer stack: diffusion, poly, contacts, metal layers

Part 2: Layout your first design

Design a CMOS inverter or NAND gate in Xschem first
Draw its complete layout in Magic using SKY130 PDK layers
Place NMOS and PMOS transistors, draw all metal connections, add all contacts and vias
Run a DC simulation from your extracted netlist in ngspice — verify it matches your schematic simulation

Part 3: DRC

Run DRC (Design Rule Check) and read the error report
Resolve every violation before moving to A11
Understand what each DRC rule is protecting against physically: minimum spacing, minimum width, enclosure rules

Resources:

A11. LVS + Post-Layout Simulation

Objective: Verify your layout matches your schematic, then observe how parasitics degrade real performance
Prerequisite: A10

Part 1: LVS

LVS compares your physical layout against your schematic netlist. It answers: does the thing I drew match the thing I designed?

Run LVS using netgen on your A10 layout
Read and interpret the full error report, every error tells you something specific
Fix all mismatches: missing connections, wrong device dimensions, unintended shorts, missing ports
Iterate until fully LVS clean
For each error you fix, note why it happened

Part 2: Post-Layout Simulation

Extract the full RC parasitic netlist from your layout using Magic/netgen
Add the extracted netlist into your ngspice testbench alongside the original schematic netlist
Run both simulations and overlay results. Compare gain, bandwidth, phase margin
Quantify the degradation: how much does gain drop? How much does bandwidth shift?
Experiment with layout modifications that reduce parasitics

What to understand: Pre-layout simulation is always optimistic. Parasitic capacitances reduce bandwidth. Parasitic resistances reduce gain. Layout quality directly determines circuit performance.

Resources:

netgen LVS tool

A12. Translinear Circuits

Objective: Understand how the exponential I–V characteristic of BJTs and weak-inversion MOSFETs enable elegant current-mode computation
Prerequisite: A5, A6

The translinear principle is one of the most beautiful ideas in analog design. It says: in a loop of forward-biased junctions, the product of currents flowing in one direction equals the product of currents flowing in the other. This falls directly out of the $I_C = I_S e^{V_{BE}/V_T}$ relationship from Task 0.8.

Part 1 — The Translinear Principle

State the translinear loop principle formally: $\prod_{CW} I_k = \prod_{CCW} I_k$ for a loop of junctions traversed clockwise and counterclockwise
Derive it from the KVL around a loop of $V_{BE}$ junctions and the exponential I–V law
Understand why this only works cleanly in the exponential regime (BJT active region, or MOSFET subthreshold)

Part 2 — Classic Translinear Circuits

Study and hand-analyse the following:

Current squarer / square-rooter: a 4-transistor translinear loop that computes $I_{out} = I_{in}^2 / I_{ref}$
Gilbert multiplier core: how two differential pairs in a translinear arrangement multiply two input currents — the basis of every analog multiplier and mixer

For each circuit:

Identify the translinear loop and write the loop equation
Derive the input-output current relationship by hand
Simulate in ngspice using BJT models. Verify the transfer function.

Part 3 — Layout

Layout the current squarer in Magic
Achieve DRC and LVS clean status
Run post-layout simulation and compare with pre-layout

Resources:

Barrie Gilbert, "Translinear circuits: a proposed classification", Electronics Letters, 1975
Razavi, "Design of Analog CMOS Integrated Circuits", 2nd Ed. — Chapter on current mirrors and log-domain circuits
Eric Vittoz's work on weak-inversion MOSFET translinear circuits

A13. Designing a Real Analog Block

Objective: Apply everything from Level 1 and Level 2 to design a complete, non-trivial analog circuit
Prerequisite: A10, A11, A12

This is the design task that pulls everything together. By now you understand transistors, current mirrors, cascodes, differential pairs, frequency response, layout, LVS, and post-layout simulation. Pick a design that demands all of it.

Choose one of the following or propose your own (get it approved first):

Folded cascode OTA — Operational transconductance amplifier using the folded cascode topology from A4. Higher performance than a two-stage op-amp in many applications. Harder to bias correctly.
Bandgap voltage reference — Temperature-independent voltage reference using PTAT and CTAT current cancellation. Requires careful device sizing, corner simulation across temperature, and understanding of $V_{BE}$ temperature coefficients. Attempt only after completing the two-stage op-amp.
Current references
LDOs For your chosen design:
Design and simulate fully in Xschem/ngspice: DC operating point, AC response, transient behaviour, frequency response
Write a proper testbench with stimulus and measurement scripts
Characterise across temperature corners (-40°C to 125°C) and supply voltage corners (±10%)
Document your design decisions: why each W/L ratio, why each bias current, what the trade-offs were

A14. Layout, DRC, LVS — Full Design

Objective: Take your A13 design through the complete physical design and verification flow
Prerequisite: A13

This is the same flow as A10 and A11 but now applied to a real, non-trivial design. The complexity is significantly higher. Multi-stage circuits introduce new LVS challenges. Larger layouts mean more DRC violations. Parasitic coupling between stages becomes a real concern.

Draw the complete layout of your A13 design in Magic VLSI
Achieve DRC clean status — no violations
Achieve LVS clean status — layout matches schematic exactly
Extract parasitics and run post-layout simulation
Compare pre- and post-layout performance — document degradation and how you addressed it
Pay attention to layout techniques: common-centroid matching for differential pairs, shielding sensitive nodes, minimising interconnect between stages

A15. Tape It Out — Tiny Tapeout

Objective: Submit your analog design to real silicon via Tiny Tapeout
Prerequisite: A14

Tiny Tapeout is a multi-project chip shuttle service that makes ASIC fabrication accessible. Your design gets a real slot on a real wafer fabricated in the SkyWater 130nm process.

Tasks

Prepare your GDS and LEF files from Magic for Tiny Tapeout submission
Write complete design documentation:
- Block diagram
- Schematic with annotated operating points
- Simulation results — pre-layout and post-layout overlaid
- Corner simulation summary
- Pin description table
- Known limitations and what you would improve
Submit to the next available Tiny Tapeout analog shuttle

Platform: Documentation / Design Review

Deliverables / Outcomes:

Conceptual design review document (2-3 pages) addressing:
- I/O pad design and ESD protection requirements
- System-level power distribution and thermal management
- Clock distribution and skew management
- Manufacturing test and assembly considerations
- How multiple SPI controllers would integrate (area, power, I/O pins, thermal)
- Key limiting factors (area, power, pins, or thermal?)
Simplified power/clock distribution sketches (conceptual level)
Lessons learned from core controller design applied to full-chip context

Mixed Signal Group Task

When: End of Level 2. Who: One group comprising students from both the Analog and Digital tracks. Format: Collaborative. Analog students own the analog blocks. Digital students own the digital blocks. Everyone understands the full system. And perform Co-simulation

MS1. Mixed Signal Design — Co-simulation

Objective: Design and verify a mixed-signal system as a team using analog-digital co-simulation
Approach: ngspice (analog) + iverilog (digital) via ngspice-shared interface

Mixed-signal design is where analog and digital blocks coexist in the same system and have to talk to each other correctly. Before attempting a full tape-out, the group will first build and verify the system entirely in co-simulation — the same methodology used in professional mixed-signal verification, just with open-source tools.

Why co-simulation first

Taping out a mixed-signal chip is genuinely hard. Floorplanning, power domain separation, analog shielding, and GDS-level integration all compound on top of already-complex designs. Co-simulation lets the group verify that the system architecture actually works — that the interface is correctly defined, timing is right, and both blocks agree — before committing to that complexity. Get the system right first. Tape it out later if the group wants to go further.

Why this is a group task

Analog designers understand transistors, operating points, parasitics, and noise. Digital designers understand RTL, timing, state machines, and synthesis. A mixed-signal system needs both. Different people own different blocks, but everyone has to understand how the full system fits together.

Suggested designs

PWM DAC: A Verilog PWM generator (digital) driving an RC reconstruction filter (analog). Verify the reconstructed analog output in co-simulation.
Simple SAR ADC: A successive approximation register FSM (digital) controlling a comparator and DAC (analog). Implement and verify the full conversion cycle.
Ring oscillator with digital frequency counter: An analog ring oscillator (Xschem/ngspice) whose output is measured by a Verilog counter (iverilog). Verify measured frequency matches simulated oscillator frequency.

Tasks

System design — full group:

Define the interface: voltage levels, timing requirements, power domains
Draw a system block diagram that all members agree on before anyone writes a line of code or schematic
Identify interface risks: digital switching noise into the analog block, signal level compatibility, timing margins

Analog subgroup:

Design and simulate analog blocks in Xschem/ngspice using SKY130 PDK models
Define clear input/output ports that the digital block will drive and read
Characterise the analog block: what input levels and timing does it need?

Digital subgroup:

Design and simulate digital blocks in Verilog using iverilog/GTKWave
Write a standalone testbench verifying the digital block in isolation
Apply formal verification (D5) to prove critical properties of the digital control logic

Co-simulation — full group:

Set up ngspice-shared co-simulation: iverilog drives the digital side, ngspice drives the analog side, values exchanged at each timestep
Run full system simulation end-to-end — not blocks in isolation
Verify the system meets specification: correct output, correct timing, no unexpected block interaction
Inject digital switching noise into the analog simulation — observe and document its effect

Documentation — full group:

System block diagram with interface specification
Analog block: schematic, simulation results, port characterisation
Digital block: RTL, testbench coverage summary, formal verification results
Co-simulation waveforms showing the full system working end-to-end
What you would do differently, and what the path to a tape-out would look like

Resources:

VLSI-FG-001

Jump to:

Level 1

Task 0.1: Linux Basics & LibreCell/aicex Installation

Digital

Analog

Task 0.2: SPI Protocol Fundamentals

Task 0.3: Architecture & Block Design

Task 0.4: Port & Signal Specification

Task 0.5: FSM & Control Logic Design

Task 0.6: RTL Translation

Task 0.7: The PN Junction and Diode

Theory

Simulation

Deliverables

Task 0.8: The BJT

Theory

Simulation

Deliverables

Task 0.9: The MOSFET

Task 0.10: Second-Order MOSFET Effects

Channel Length Modulation

Velocity Saturation

Body Effect

Subthreshold Conduction

Mismatch (Pelgrom)

Deliverables

Task 0.11: The CMOS Inverter

Theory

Simulation

Task 0.12: Introduction to Operational Amplifiers

Part 1 — Theory

Part 2 — Simulation

Level 2

Level 1 — Analog Track: Deep circuit intuition

A1. First Steps: MOS Amplifiers

Setup

Task

Common-Source (CS) Amplifier

Common-Gate (CG) Amplifier

Common-Drain (CD) Amplifier — Source Follower

Comparison

A2. CS Amplifier Variants

A3. Current Mirrors

Tasks

A4. Cascode Amplifiers

Tasks

Part 1 — Telescopic Cascode

Part 2 — Folded Cascode

A5. Differential Amplifiers

Tasks

Part 1 — Basic Differential Pair

Part 2 — Differential Pair with Active Load

Part 3 — Analysis

A6. Negative Feedback Systems

Part 1 — The Feedback Framework

Part 2 — Stability

Part 3 — Connecting Back to Circuits

A7. Frequency Response

Tasks

Part 1 — Poles and Zeros

Part 2 — Miller Effect

Part 3 — Frequency Response of the Differential Pair

A8. Op-Amps — For Real This Time

Part 1 — The Two-Stage Op-Amp

Part 2 — Compensation

Part 3 — Closed-Loop Behaviour

A9. Stability, Compensation, and Noise

Part 1: Stability and Dominant Pole Compensation

Part 2: Noise Fundamentals

Level 1 — Digital Track: RTL Verification & Synthesis

D1. Functional Verification with Testbenches

D2. Formal Verification with Z3/SAT Solver

D3. PDK Selection & Technology Understanding

D4. LibreLane Configuration File

D5. Synthesis & Timing Analysis

Level 3

Level 2 Analog Track: Layout and Tapeout

A10. Magic! Your First Layout

Part 1: Learn Magic