Low Power Design techniques in FPGA

What are FPGAs?

Field-programmable gate arrays are ideal for adaptive systems, since they are reconfigurable and can be programmed to implement any digital logic.

FPGAs are extremely versatile. They allow developers to test any number of variables after the board is built. When changes are required, new configuration files are transferred onto the device that make new functionality available

FPGAs are made up of-

• CLB(Configurable Logic Block) : Implements logic part of digital circuit.
• Configurable routing fabric : Implements the connections between the logic blocks
• Memories
• ALU

Power Dissipation in FPGA -

--> Static Power -

• Also known as Leakage Power
• Consumed when FPGA is idle
• Arises primarily from leakage currents in transistors, which occur even when the circuit is not actively switching.

--> Dynamic Power -

• Consumed during the operation of FPGA
• Primarily due to switching
• Dynamic power can be broken down further into switching power, which is the power consumed by charging and discharging capacitors in the circuit, and short-circuit power, which occurs during the brief period when both the pull-up and pull-down transistors are conducting.

The image below shows the breakdown of core power consumptionin a commercial 90nm FPGA -

Low Power Design techniques-

1. Clock Gating- Clock gating is a technique used to reduce power consumption by disabling the clock signal to inactive modules within the FPGA. By gating the clock, engineers can prevent unnecessary switching activity, which directly reduces dynamic power consumption. This technique is well-known and well supported in most tools and flows.

2. Pipelining- Pipelining is a simple and effective way of reducing glitching, and hence minimising power consumption. It is found that, at a given clock speed, pipelining can reduce the amount of energy per operation by between 40% and 90% for applications such as FIR Filters.

3. Dynamic Voltage scaling- Dynamic voltage scaling can be used to adapt the supply voltage to the FPGA as the temperature changes, to minimise power consumption. It has been shown that power reduction between 4% and 54% can be achieved for various arithmetic circuits.

4. Technology Mapping- the process of selecting the appropriate logic cells from the FPGA’s library to implement the design. By choosing low-power library cells, engineers can reduce the static and dynamic power consumed by the logic circuits.

5. Hierarchical State Machines- Hierarchical state machines can be structured to isolate low-power states. By designing the state machine to enter these low-power states during periods of inactivity, static and dynamic power consumption can be minimized.

6. State Encoding- The way states are encoded in the state machine can also impact power consumption. By choosing state encodings that minimize switching activity, engineers can reduce dynamic power.

7. Data Encoding- Efficient data encoding schemes, such as Gray code, can be used to reduce switching activity in the data path. By minimizing the number of transitions between consecutive data values, the dynamic power consumed by the data path can be reduced.

8. Power Gating- This is a technique where functions on an IC are also partitioned. Power gating effectively shuts off the power completely for a block. In the power equation, this zeros out the voltage and shuts off power, resulting in both static and dynamic savings for the time that the block is turned off. Power gating typically offers the most aggressive power savings, and thus it’s an ideal goal to shut off as many domains as possible, as often as possible, while maintaining functionality.

9. Bus Encoding- Encoding the signals on buses, which are used to transfer data between different parts of the FPGA, can further reduce switching activity. Techniques such as bus-invert encoding can be applied to minimize the number of transitions on the bus, thereby reducing the power consumed during data transfers.

10. Multi Voltage- This is a technique where functions of a chip are partitioned via performance characteristics – perhaps one block is high performance, while the rest of the chip is lower performance. To achieve the goals for the high-performance block, a higher voltage is typically required; while to save power on the lower performance blocks, a lower voltage can be used. This is in lieu of designing the entire block at the higher voltage, which is simpler but more power intensive.

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