TASK 9 : Your Logic, Preloaded

A lookup table (LUT) is a programmable way to perform digital logic functionality .The LUT is implemented using memory (like a ROM or RAM) to store the output values for each input combination. It essentially stores the results of a logic function for all possible input combinations in a table, allowing for fast retrieval of the output without requiring complex logic gates.

Advantages -

• LUTs can implement any logic function by simply modifying the stored values in the memory.
• LUTs offer fast logic execution, as they rely on memory access rather than gate delays. 
• In FPGAs, LUTs are a programmable way to implement logic functions, allowing for flexible designs.

Lookup tables might seem the same as truth tables, but there are certain differences between them.

Difference between Lookup table and Truth table -

Truth Table- It is a conceptual tool used to define the behavior of a logic function, listing all possible input combinations and their corresponding outputs.

Lookup Table- It is a physical memory structure (like in an FPGA) that stores these pre-defined mappings and can be directly accessed to retrieve the output for a given input.

The truth table for 2 input XOR gate is -

Working : A 4x1 LUT works like a 4-entry memory (a ROM):

• It has 2 selection bits (A, B), which form a 2-bit address (00, 01, 10, 11).
• It has 4 data inputs (I0 to I3), which store constant values (the outputs for each address).
• The selected output is based on the address formed by the 2 inputs.

For XOR, we have :

• If A=0, B=0 → output = 0 → I0 = 0
• If A=0, B=1 → output = 1 → I1 = 1
• If A=1, B=0 → output = 1 → I2 = 1
• If A=1, B=1 → output = 0 → I3 = 0

Since Logisim doesn’t have a native 4x1 LUT component, we use a 4-input multiplexer to simulate it.

Click here to view the working of the circuit

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TASK 10 : Whose Array is it Anyway?

PROM -

PROM(Programmable Read Only Memory) is a type of non-volatile memory which means once programmed retains its data permanently.

Block diagram of PROM -

• In PROM, AND gates are fixed and OR gates are programmable.
• It is used in Radio-Frequency Identification (RFID)tags, High definition Multimedia Interfaces(HDMI)
• Few advantages include it's non dependency on difficult wiring of the program to the chip and that PROM can retrieve data even when the power is turned off, confirming that important information is not lost.

PAL -

The Programmable Array Logic (PAL) is a programmable logic device that allows the implementation of the combinational logic circuits with the fixed OR array and a programmable AND array. The PALs are commonly used in digital systems for the creating custom logic circuits efficiently.

Advantages -

• Highly efficient
• Low production cost as compared to PLA
• Highly secure
• More flexible to design.

Disadvantages -

• Limited flexibility as compared to FPGAs
• PAL devices may have a limited number of logic gates and inputs thereby causing size constraints
• The fixed structure of the OR array may introduce propagation delays.

Applications -

• Digital Signal Processing
• Control Systems
• Embedded systems

PLA -

A Programmable Logic Array (PLA) is the implementation of the combinational logic circuits using a programmable type of a digital logic device. There is a programmable AND gate array with a programmable OR gate.

Advantages -

• Both the programmable AND and OR gates offer the benefits of being used in a number of combinational circuits.
• It will only implement the necessary minterms thus making the design compact and more efficient.
• The PLAs can be reconfigured to perform different logic functions

Disadvantages -

• The usage of PLAs is a little complicated due to their high flexibility.
• It has higher cost as compared to PALs

Applications -

• BUS interface in programmed I/O
• decoder
• counter

Difference between PROM, PAL and PLA -

PROM - Fixed AND gate array, Programmable OR gate array.

PLA - Programmable AND gate, Programmable OR gate.

PAL - Programmable AND gate, Fixed OR gate

Task 1 -

1. The task involves designing a logic circuit that gives output '1' if the number of 1's in a 3 bit input (A, B and C) is odd using a PAL and PLA.
2. This is basically the implementation of XOR gate since XOR gate outputs '1' if the number of 1's in its inputs is odd.
3. The Boolean expression is F = A ⊕ B ⊕ C = A'B'C + A'BC' + AB'C' + ABC .

The truth table is given :

Design using PAL -

FUSE TABLE -

X - means a fuse connection and Blank - means a blown connection

Below is the implementation of the design using PAL -

Design using PLA -

FUSE TABLE -

X - means a fuse connection and Blank - means a blown connection

Below is the implementation of the design using PLA -

Click here to view the simulation of the design

Task 2 -

To design a controller that manages three lights in a smart home system based on these conditions - Motion sensor (M), Light level sensor (L), Time of day (T), Manual override (O) - using either PLA or PAL and justify the design.

INPUTS -

• M: Motion sensor (1 = motion detected, 0 = no motion)
• L: Light level sensor (1 = bright, 0 = dark)
• T: Time of day (1 = night, 0 = day)
• O: Manual override (1 = ON, 0 = OFF)

OUTPUTS -

• L1: Light 1 (e.g., hallway)
• L2: Light 2 (e.g., living room)
• L3: Light 3 (e.g., exterior/front porch)

Behavior based on Inputs -

1. Light 1 (L1 - Hallway): Turn ON if:
   • Motion detected (M=1) AND
   • It is dark (L=0) AND
   • It's night (T=1)

• OR Manual override is ON (O=1)

1. Light 2 (L2 - Living Room): Turn ON if:
   • Manual override is ON (O=1)

• OR Motion is detected (M=1) AND it is dark (L=0)

1. Light 3 (L3 - Porch Light): Turn ON if:
   • It is night (T=1)

• OR Manual override is ON (O=1)

Design using PLA -

Reason -

• A PLA offers flexibility in programming both AND and OR arrays.
• Better suited for customizable logic with shared product terms across multiple outputs (L1, L2, L3).

Product terms :

• P1 = ML'T → for L1
• P2 = O → for L1, L2, L3
• P3 = ML' → for L2
• P4 = T → for L3

Output Equations :

• L1 = P1 + P2 = (ML'T) + O
• L2 = P2 + P3 = O + (ML')
• L3 = P2 + P4 = O + T

Click here to view the simulation

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Mechanical Design

TASK 1 : Isometric and Orthographic Projections

Orthographic Projections -

Below is orthographic projections in third angle projection with Top View, Front View and Side view :

1. 

1. 

Isometric Projections -

Below is the image of isometric projection -

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TASK 2 : 2 D Drafting

The Sierpinski triangle is a fractal created by repeatedly removing the middle triangle from an equilateral triangle. This process is repeated infinitely, resulting in a shape with self-similar patterns at different scales.

A level-2 Sierpinski triangle is created by starting with a larger triangle and repeating the process of removing the central triangle from each smaller triangle. At level 2, you will have 9 triangles remaining within the original larger triangle

Steps -

1. Begin with a large equilateral triangle.
2. Find the midpoints of each side of the triangle and connect them.
3. Repeat the same steps until 9 smaller triangles pointing upwards are left.

Below is the diagram of Level 2 -

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TASK 3 : 2D drawings in CAD

Below is the image of one of the 2D drawings in the given folder drawn using Auto CAD :

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